If the associativity of a processor cache is doubled while keeping the capacity and block size unchanged, which one of the following is guaranteed to be NOT affected?

Let:

• $C =$ Cache capacity (in bytes)

• $B =$ Block size (in bytes)

• $P =$ Associativity ($P$-way set associative)

• Number of lines $N = \frac{C}{B}$

• Number of sets $S = \frac{N}{P} = \frac{C}{P \times B}$

When associativity $P$ is doubled to $2P$ while keeping $C$ and $B$ unchanged:

1. Number of sets $S$ is halved: The number of set index bits becomes $\log_2(S) - 1$, decreasing by $1$ bit. Thus, the width of the set index decoder changes (is affected).

2. Tag field width: Tag bits = $\text{Address bits} - \text{Set index bits} - \text{Block offset bits}$. As set index bits decrease by $1$, tag bits increase by $1$. Hence, the width of the tag comparator increases by $1$ bit (is affected).

3. Way selection multiplexor: Since the number of ways is doubled, the multiplexor needs to select from $2P$ ways instead of $P$ ways, so its size/width is affected.

4. Processor to main memory data bus width: The width of the system data bus between processor/cache and main memory is determined by the memory architecture and memory interface standards, and is completely independent of internal cache associativity.

Thus, the width of processor to main memory data bus is guaranteed to be NOT affected.