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Computer Organization and Architecture · Cache Memory and Hierarchy
Official IIT answer key · IIT Kharagpur · Audited Aug 2026
GATE CSE 2014 Set 2 Q44 · MCQ · 2 marks
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Topic notes
Memory hierarchy and cache mapping is one of the highest-yield, most quantitative topics in GATE Computer Science, regularly tested through 2-mark NAT and MSQ questions. GATE focuses heavily on bit-level address field decomposition (Tag, Set/Line Index, Block Offset) across direct, set-associative, and fully-associative caches, as well as multi-level hierarchical Average Memory Access Time (AMAT) calculations. Recent years have increased the emphasis on multi-select questions (MSQs) tracing reference sequences for eviction behavior and comparing write-back versus write-through policies.
Full Cache Memory and Hierarchy guide →If the associativity of a processor cache is doubled while keeping the capacity and block size unchanged, which one of the following is guaranteed to be NOT affected?
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