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I/O Interface, Interrupts and DMA

GATE CSE 2013 · Q28

MCQ2 marksEasy

Time

Consider the following sequence of micro-operations. MBR ←\leftarrow PC MAR ←\leftarrow X PC ←\leftarrow Y Memory ←\leftarrow MBR Which one of the following is a possible operation performed by this sequence?

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Solution

Step-by-step verified solution

Official answer: D) Initiation of interrupt service

I/O Interface, Interrupts and DMA

Let us analyze the micro-operations step-by-step:

  1. MBR←PC\text{MBR} \leftarrow \text{PC}: The current content of the Program Counter (PC), which is the return address, is moved to the Memory Buffer Register (MBR).

  2. MAR←X\text{MAR} \leftarrow \text{X}: A memory location X\text{X} (such as a stack pointer or reserved vector address) is loaded into the Memory Address Register (MAR).

  3. PC←Y\text{PC} \leftarrow \text{Y}: The starting address Y\text{Y} of the Interrupt Service Routine (ISR) is loaded into the PC.

  4. Memory←MBR\text{Memory} \leftarrow \text{MBR}: The return address stored in MBR is saved to memory at address X\text{X}.

This sequence of saving the return address and branching to the ISR address is the standard procedure for the Initiation of interrupt service.

Hence, option (D) is correct.

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This I/O Interface, Interrupts and DMA previous year question is Q28 of the GATE CSE 2013 paper. Find more GATE CSE PYQs on I/O Interface, Interrupts and DMA in Computer Organization and Architecture, or browse all GATE CSE PYQs.

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I/O Interface, Interrupts and DMA in GATE CSE

I/O Interface, Interrupts and DMA has 13 GATE CSE PYQs across 12 papers from 2011 to 2026. 2 of them are 2-mark MCQs like this one, and it is the only one in GATE CSE 2013.

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GateAI solution cardGATE CSE 2013 · Q28 · MCQ

Consider the following sequence of micro-operations. MBR PC MAR X PC Y Memory MBR Which one of the following is a possible operation performed by this sequence?

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Independent practice explanation verified by the GateAI team. GATE is conducted by the IITs; question text follows the official paper.