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Computer Organization and Architecture · I/O Interface, Interrupts and DMA
Official IIT answer key · IIT Bombay · Audited Aug 2026
GATE CSE 2013 Q28 · MCQ · 2 marks
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Topic notes
GATE tests I/O interface (Interrupt and DMA) across two main facets: conceptual understanding of I/O transfer mechanisms (Programmed I/O, Interrupt-driven I/O, and DMA modes) alongside quantitative calculations on DMA bandwidth, cycle stealing, and register limits. Conceptual questions regularly assess interrupt lifecycle events, priority resolution (Daisy chaining vs Polling), and vectored vs non-vectored interrupt handling. Numerical questions focus on DMA throughput given processor clock frequency and stolen cycle percentages, as well as transfer chunking governed by DMA data counter bit-widths.
Full I/O Interface, Interrupts and DMA guide →Consider the following sequence of micro-operations. MBR PC MAR X PC Y Memory MBR Which one of the following is a possible operation performed by this sequence?
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