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I/O Interface, Interrupts and DMA

GATE CSE 2025 Set 1 · Q11

MCQ1 markEasy

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Suppose a program is running on a non-pipelined single processor computer system. The computer is connected to an external device that can interrupt the processor asynchronously. The processor needs to execute the interrupt service routine (ISR) to serve this interrupt. The following steps (not necessarily in order) are taken by the processor when the interrupt arrives: (i) The processor saves the content of the program counter. (ii) The program counter is loaded with the start address of the ISR. (iii) The processor finishes the present instruction. Which ONE of the following is the CORRECT sequence of steps?

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Official answer: A) (iii), (i), (ii)

I/O Interface, Interrupts and DMA

When an asynchronous interrupt request is received by a non-pipelined processor during the execution of a program, the processor handles it in the following sequence:

  1. Step (iii): The processor checks for interrupts at the end of the current instruction cycle and allows the currently executing instruction to complete.

  2. Step (i): To enable resuming execution of the interrupted program later, the return address (the updated content of the Program Counter, along with processor status flags) is saved onto the stack.

  3. Step (ii): The Program Counter (PC) is updated with the starting address of the Interrupt Service Routine (ISR) to begin fetching and executing ISR instructions.

Therefore, the correct chronological sequence is (iii), (i), (ii), which corresponds to option (A).

*(Note: Options C and D continue onto the next page and are omitted due to page cut-off.)*

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This I/O Interface, Interrupts and DMA previous year question is Q11 of the GATE CSE 2025 Set 1 paper. Find more GATE CSE PYQs on I/O Interface, Interrupts and DMA in Computer Organization and Architecture, or browse all GATE CSE PYQs.

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I/O Interface, Interrupts and DMA in GATE CSE

I/O Interface, Interrupts and DMA has 13 GATE CSE PYQs across 12 papers from 2011 to 2026. 8 of them are 1-mark MCQs like this one, and it is the only one in GATE CSE 2025 Set 1.

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GateAI solution cardGATE CSE 2025 Set 1 · Q11 · MCQ

Suppose a program is running on a non-pipelined single processor computer system. The computer is connected to an external device that can interrupt the processor asynchronously. The processor needs to execute the interrupt service routine (ISR) to serve this interrupt. The following steps (not necessarily in order) are taken by the processor when the interrupt arrives: (i) The processor saves the content of the program counter. (ii) The program counter is loaded with the start address of the ISR. (iii) The processor finishes the present instruction. Which ONE of the following is the CORRECT sequence of steps?

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Independent practice explanation verified by the GateAI team. GATE is conducted by the IITs; question text follows the official paper.