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I/O Interface, Interrupts and DMA

GATE CSE 2026 Set 2 · Q18

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Consider the following two statements about interrupt handling mechanisms in a CPU. S1: In non-vectored interrupt mechanism, it usually takes more time to start the Interrupt Service Routine (ISR) when compared to that in a vectored interrupt mechanism. S2: In daisy-chain interrupt mechanism, the CPU polls all the input devices individually to determine the source of the interrupt. Which one of the following options is correct with respect to S1 and S2 ?

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Solution

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Official answer: C) S1 is true and S2 is false

I/O Interface, Interrupts and DMA

To determine the correctness of statements S1 and S2:

  1. Statement S1 is True:

    • In a vectored interrupt, the interrupting device provides the interrupt vector (or direct address) to the CPU over the bus, allowing the CPU to immediately jump to the device's specific Interrupt Service Routine (ISR).

    • In a non-vectored interrupt, the CPU branches to a fixed memory address common to all interrupts. The general interrupt handler must then determine the identity of the requesting device (often via software polling) before invoking the specific ISR. This additional software overhead results in a longer latency to start the specific ISR.

  2. Statement S2 is False:

    • The daisy-chain mechanism is a hardware-based priority resolution method. When an interrupt is acknowledged, the CPU sends an interrupt acknowledge signal (INTAINTA) that passes serially from one device to the next through the hardware chain until the requesting device captures it and puts its vector on the data bus. The CPU does not poll devices individually in software.

    • Software polling is a separate software-based mechanism where the CPU sequentially checks status registers of each I/O device.

Therefore, S1 is true and S2 is false, which corresponds to option (C).

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This I/O Interface, Interrupts and DMA previous year question is Q18 of the GATE CSE 2026 Set 2 paper. Find more GATE CSE PYQs on I/O Interface, Interrupts and DMA in Computer Organization and Architecture, or browse all GATE CSE PYQs.

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I/O Interface, Interrupts and DMA in GATE CSE

I/O Interface, Interrupts and DMA has 13 GATE CSE PYQs across 12 papers from 2011 to 2026. 8 of them are 1-mark MCQs like this one, and it is the only one in GATE CSE 2026 Set 2.

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GateAI solution cardGATE CSE 2026 Set 2 · Q18 · MCQ

Consider the following two statements about interrupt handling mechanisms in a CPU. S1: In non-vectored interrupt mechanism, it usually takes more time to start the Interrupt Service Routine (ISR) when compared to that in a vectored interrupt mechanism. S2: In daisy-chain interrupt mechanism, the CPU polls all the input devices individually to determine the source of the interrupt. Which one of the following options is correct with respect to S1 and S2 ?

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Independent practice explanation verified by the GateAI team. GATE is conducted by the IITs; question text follows the official paper.