Computer Organization and Architecture · Instruction Pipelining
Official IIT answer key · IISc Bangalore · Audited Aug 2026
GATE CSE 2024 Set 2 Q31 · MSQ · 1 mark
I1: DIV R3, R1, R2I2: SUB R5, R3, R4I3: ADD R3, R5, R6I4: MUL R7, R3, R8
Which of the following statements is/are TRUE?Key concept
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Topic notes
Instruction pipelining and pipeline hazards are tested extensively with a heavy numerical skew (primarily 2-mark NATs). GATE focuses on evaluating effective CPI and speedup under realistic hazard scenarios (data, control, and structural), calculating clock cycle time from bottleneck stage delays and latch latencies, and analyzing cycle-by-cycle instruction progression with or without operand forwarding. Conceptual items frequently test dependency classifications (RAW, WAR, WAW) and the mechanics of operand bypassing.
Full Instruction Pipelining guide →An instruction format has the following structure: Instruction Number: Opcode destination reg, source reg-1, source reg-2 Consider the following sequence of instructions to be executed in a pipelined processor: I1: DIV R3, R1, R2 I2: SUB R5, R3, R4 I3: ADD R3, R5, R6 I4: MUL R7, R3, R8 Which of the following statements is/are TRUE?
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