A processor $X_1$ operating at 2 GHz has a standard 5-stage RISC instruction pipeline having a base CPI (cycles per instruction) of one without any pipeline hazards. For a given program P that has 30% branch instructions, control hazards incur 2 cycles stall for every branch. A new version of the processor $X_2$ operating at same clock frequency has an additional branch predictor unit (BPU) that completely eliminates stalls for correctly predicted branches. There is neither any savings nor any additional stalls for wrong predictions. There are no structural hazards and data hazards for $X_1$ and $X_2$. If the BPU has a prediction accuracy of 80%, the speed up (*rounded off to two decimal places*) obtained by $X_2$ over $X_1$ in executing P is _________.

Let the number of instructions in program P be $I$, and the clock cycle time be $T_{\text{clk}}$. Both processors operate at the same clock frequency ($2\text{ GHz}$).

1. Average CPI for processor $X_1$:

   • Base $\text{CPI} = 1$

   • Branch instructions $= 30\% = 0.30$

   • Each branch causes $2$ stall cycles.

   $$\text{CPI}_1 = 1 + (0.30 \times 2) = 1 + 0.60 = 1.60$$

2. Average CPI for processor $X_2$:

   • Accuracy $= 80\% \implies$ Misprediction rate $= 100\% - 80\% = 20\% = 0.20$

   • Correct predictions incur $0$ stalls; mispredictions incur $2$ stalls.

   • Average stall cycles per branch $= 0.20 \times 2 = 0.40$

   $$\text{CPI}_2 = 1 + (0.30 \times 0.40) = 1 + 0.12 = 1.12$$

3. Speedup of $X_2$ over $X_1$:

   $$\text{Speedup} = \frac{\text{Execution Time of } X_1}{\text{Execution Time of } X_2} = \frac{\text{CPI}_1}{\text{CPI}_2} = \frac{1.60}{1.12} = \frac{10}{7} \approx 1.4286$$

Rounding off to two decimal places gives 1.43 (accepted range: 1.42 to 1.45).