The EX stage of a pipelined processor performs the memory read operations for LOAD instructions, and the operations for the arithmetic and logic instructions. Let $t_{EX}$ denote the time taken by the EX stage to perform the operation for an instruction. For each instruction type, the values of $t_{EX}$ and $M$ (the number of instructions of that type in a sequence of 100 instructions for a program P), are given in the table below. The duration of the pipeline clock cycle is 1 nanosecond. Assume that the latch time for the interstage buffers in the pipeline is negligible. When program P is executed, the number of clock cycles for which the pipeline is stalled due to structural hazards in the EX stage is ________. (answer in integer)

Since the clock cycle duration is $1\text{ ns}$, an instruction requiring $t_{EX}$ nanoseconds in the EX stage takes $\lceil t_{EX} / 1\text{ ns} \rceil = \lceil t_{EX} \rceil$ clock cycles.

Whenever an instruction occupies the EX stage for $k > 1$ cycles, the subsequent instruction cannot enter the EX stage for $k - 1$ cycles, leading to $k - 1$ stall cycles per instruction due to structural hazard.

Calculating stalls for each instruction type:

1. LOAD: $t_{EX} = 1.8\text{ ns} \implies \lceil 1.8 \rceil = 2$ cycles $\implies 2 - 1 = 1$ stall cycle.

   $$\text{Stalls} = 15 \times 1 = 15$$

2. IMUL: $t_{EX} = 1.5\text{ ns} \implies \lceil 1.5 \rceil = 2$ cycles $\implies 2 - 1 = 1$ stall cycle.

   $$\text{Stalls} = 10 \times 1 = 10$$

3. IDIV: $t_{EX} = 2.5\text{ ns} \implies \lceil 2.5 \rceil = 3$ cycles $\implies 3 - 1 = 2$ stall cycles.

   $$\text{Stalls} = 5 \times 2 = 10$$

4. FADD: $t_{EX} = 1.7\text{ ns} \implies \lceil 1.7 \rceil = 2$ cycles $\implies 2 - 1 = 1$ stall cycle.

   $$\text{Stalls} = 10 \times 1 = 10$$

5. FSUB: $t_{EX} = 1.7\text{ ns} \implies \lceil 1.7 \rceil = 2$ cycles $\implies 2 - 1 = 1$ stall cycle.

   $$\text{Stalls} = 5 \times 1 = 5$$

6. FMUL: $t_{EX} = 2.8\text{ ns} \implies \lceil 2.8 \rceil = 3$ cycles $\implies 3 - 1 = 2$ stall cycles.

   $$\text{Stalls} = 15 \times 2 = 30$$

7. FDIV: $t_{EX} = 3.2\text{ ns} \implies \lceil 3.2 \rceil = 4$ cycles $\implies 4 - 1 = 3$ stall cycles.

   $$\text{Stalls} = 5 \times 3 = 15$$

8. All other instructions: $t_{EX} < 1.0\text{ ns} \implies 1$ cycle $\implies 0$ stall cycles.

   $$\text{Stalls} = 35 \times 0 = 0$$

Summing all stall cycles: