A non-pipelined instruction execution unit operating at 2 GHz takes an average of 6 cycles to execute an instruction of a program P. The unit is then redesigned to operate on a 5-stage pipeline at 2 GHz. Assume that the ideal throughput of the pipelined unit is 1 instruction per cycle. In the execution of program P, 20% instructions incur an average of 2 cycles stall due to data hazards and 20% instructions incur an average of 3 cycles stall due to control hazards. The speedup (rounded off to one decimal place) obtained by the pipelined design over the non-pipelined design is ________

To calculate the speedup obtained by the pipelined design over the non-pipelined design:

1. Non-pipelined Processor:

   • Average cycles per instruction: $\text{CPI}_{\text{non-pipe}} = 6$

   • Clock frequency: $f = 2\text{ GHz}$

   • Average execution time per instruction:

     $$\text{ET}_{\text{non-pipe}} = \frac{\text{CPI}_{\text{non-pipe}}}{f} = \frac{6}{2\text{ GHz}}$$

2. Pipelined Processor:

   • Ideal $\text{CPI} = 1$

   • Stalls due to data hazards = $20\% \times 2 = 0.20 \times 2 = 0.4\text{ cycles/instruction}$

   • Stalls due to control hazards = $20\% \times 3 = 0.20 \times 3 = 0.6\text{ cycles/instruction}$

   • Average $\text{CPI}_{\text{pipe}} = 1 + 0.4 + 0.6 = 2.0$

   • Average execution time per instruction:

     $$\text{ET}_{\text{pipe}} = \frac{\text{CPI}_{\text{pipe}}}{f} = \frac{2.0}{2\text{ GHz}}$$

3. Speedup:

   $$\text{Speedup} = \frac{\text{ET}_{\text{non-pipe}}}{\text{ET}_{\text{pipe}}} = \frac{\text{CPI}_{\text{non-pipe}}}{\text{CPI}_{\text{pipe}}} = \frac{6}{2.0} = 3.0$$

Thus, the speedup is 3.0 (acceptable range: 2.9 to 3.1).