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Computer Organization and Architecture · Instruction Set and Addressing Modes
Official IIT answer key · IIT Guwahati · Audited Aug 2026
GATE CSE 2025 Set 1 Q37 · MCQ · 2 marks
ADD R1, #25 // R1 = R1 + 25Key concept
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Topic notes
Instruction set and addressing modes in GATE CS is consistently tested through instruction word encoding, expanding opcode schemes, addressing mode semantics, and ISA architectural principles. Problems evaluate a candidate's ability to calculate bit allocations for opcodes, register specifiers, and immediates, as well as mapping high-level constructs (structs, arrays, pointers) to assembly addressing modes. The topic features a healthy mix of conceptual 1-mark MCQs/MSQs and rigorous 2-mark NATs involving bit calculations and assembly program traces.
Full Instruction Set and Addressing Modes guide →A processor has 64 general-purpose registers and 50 distinct instruction types. An instruction is encoded in 32-bits. What is the maximum number of bits that can be used to store the immediate operand for the given instruction? ADD R1, #25 // R1 = R1 + 25
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