Computer Organization and Architecture · Instruction Set and Addressing Modes
Official IIT answer key · IIT Roorkee · Audited Aug 2026
GATE CSE 2026 Set 1 Q15 · MCQ · 1 mark
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Topic notes
Instruction set and addressing modes in GATE CS is consistently tested through instruction word encoding, expanding opcode schemes, addressing mode semantics, and ISA architectural principles. Problems evaluate a candidate's ability to calculate bit allocations for opcodes, register specifiers, and immediates, as well as mapping high-level constructs (structs, arrays, pointers) to assembly addressing modes. The topic features a healthy mix of conceptual 1-mark MCQs/MSQs and rigorous 2-mark NATs involving bit calculations and assembly program traces.
Full Instruction Set and Addressing Modes guide →Consider a processor P whose instruction set architecture is the load-store architecture. The instruction format is such that the first operand of any instruction is the destination operand. Which one of the following sequences of instructions corresponds to the high-level language statement Z = X + Y ? *Note:* X, Y, and Z are memory operands. R0, R1, and R2 are registers.
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