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Instruction Set and Addressing Modes

GATE CSE 2026 Set 1 · Q14

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Match each addressing mode in List I with a data element or an element of a data structure (in a high-level language) in List II:

GATE CSE 2026 Set 1 Q14 diagram

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Official answer: B) P–4, Q–2, R–1, S–3

Instruction Set and Addressing Modes

Let us analyze each mapping from List I to List II:

  • P. Immediate Addressing: The operand value is directly specified within the instruction itself as a constant literal. This corresponds to 4. Constant.

  • Q. Indirect Addressing: The address field of the instruction specifies a memory location or register holding the pointer/address of the effective operand (dereferencing). This corresponds to 2. Pointer.

  • R. Base with Index: The effective address is obtained by adding the contents of a base register and an index register (often scaled), which is standard for accessing an 1. Element of an array.

  • S. Base with offset/displacement: The effective address is computed by adding a fixed constant offset to the address in a base register, which is standard for accessing a fixed field in an 3. Element of a record (struct member).

Therefore, the correct mapping is P–4, Q–2, R–1, S–3, which corresponds to Option (B).

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This Instruction Set and Addressing Modes previous year question is Q14 of the GATE CSE 2026 Set 1 paper. Find more GATE CSE PYQs on Instruction Set and Addressing Modes in Computer Organization and Architecture, or browse all GATE CSE PYQs.

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Instruction Set and Addressing Modes in GATE CSE

Instruction Set and Addressing Modes has 19 GATE CSE PYQs across 15 papers from 2011 to 2026. 6 of them are 1-mark MCQs like this one, and GATE CSE 2026 Set 1 has 2.

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GateAI solution cardGATE CSE 2026 Set 1 · Q14 · MCQ

Match each addressing mode in List I with a data element or an element of a data structure (in a high-level language) in List II:

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Independent practice explanation verified by the GateAI team. GATE is conducted by the IITs; question text follows the official paper.