Computer Organization and Architecture · Instruction Set and Addressing Modes
Official IIT answer key · IISc Bangalore · Audited Aug 2026
GATE CSE 2024 Set 2 Q57 · NAT · 2 marks
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Instruction set and addressing modes in GATE CS is consistently tested through instruction word encoding, expanding opcode schemes, addressing mode semantics, and ISA architectural principles. Problems evaluate a candidate's ability to calculate bit allocations for opcodes, register specifiers, and immediates, as well as mapping high-level constructs (structs, arrays, pointers) to assembly addressing modes. The topic features a healthy mix of conceptual 1-mark MCQs/MSQs and rigorous 2-mark NATs involving bit calculations and assembly program traces.
Full Instruction Set and Addressing Modes guide →A processor with 16 general purpose registers uses a 32-bit instruction format. The instruction format consists of an opcode field, an addressing mode field, two register operand fields, and a 16-bit scalar field. If 8 addressing modes are to be supported, the maximum number of unique opcodes possible for every addressing mode is …
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