GateAI
Instruction Pipelining

GATE CSE 2016 Set 1 · Q32

NAT2 marksMedium

Time

The stage delays in a 4-stage pipeline are 800, 500, 400 and 300 picoseconds. The first stage (with delay 800 picoseconds) is replaced with a functionally equivalent design involving two stages with respective delays 600 and 350 picoseconds. The throughput increase of the pipeline is _________ percent.

Your answerNumerical answer

Enter a value to check

Solution

Step-by-step verified solution

Official answer: 33.33 (±0.5) (±0.5)

Instruction Pipelining
  1. Original Pipeline:

    • Number of stages = 4

    • Stage delays = 800 ps,500 ps,400 ps,300 ps800\text{ ps}, 500\text{ ps}, 400\text{ ps}, 300\text{ ps}

    • Cycle time of the original pipeline (T1T_1):

      T1=max⁡(800,500,400,300)=800 psT_1 = \max(800, 500, 400, 300) = 800\text{ ps}
    • Original throughput (Throughput1\text{Throughput}_1):

      Throughput1=1T1=1800 ps\text{Throughput}_1 = \frac{1}{T_1} = \frac{1}{800\text{ ps}}
  2. Modified Pipeline:

    • The 800 ps stage is split into two stages of 600 ps and 350 ps.

    • Stage delays = 600 ps,350 ps,500 ps,400 ps,300 ps600\text{ ps}, 350\text{ ps}, 500\text{ ps}, 400\text{ ps}, 300\text{ ps}

    • Cycle time of the new pipeline (T2T_2):

      T2=max⁡(600,350,500,400,300)=600 psT_2 = \max(600, 350, 500, 400, 300) = 600\text{ ps}
    • New throughput (Throughput2\text{Throughput}_2):

      Throughput2=1T2=1600 ps\text{Throughput}_2 = \frac{1}{T_2} = \frac{1}{600\text{ ps}}
  3. Percentage Increase in Throughput:

    Percentage Increase=(Throughput2−Throughput1Throughput1)×100%\text{Percentage Increase} = \left( \frac{\text{Throughput}_2 - \text{Throughput}_1}{\text{Throughput}_1} \right) \times 100\%
    Percentage Increase=(1600−18001800)×100%=(800600−1)×100%=(43−1)×100%=1003%≈33.33%\text{Percentage Increase} = \left( \frac{\frac{1}{600} - \frac{1}{800}}{\frac{1}{800}} \right) \times 100\% = \left( \frac{800}{600} - 1 \right) \times 100\% = \left( \frac{4}{3} - 1 \right) \times 100\% = \frac{100}{3}\% \approx 33.33\%

Try the question first, then check your work.

Think the official key or this write-up is wrong?

Report error or challenge

Examiner trap

The misconception this question tests

This Instruction Pipelining previous year question is Q32 of the GATE CSE 2016 Set 1 paper. Find more GATE CSE PYQs on Instruction Pipelining in Computer Organization and Architecture, or browse all GATE CSE PYQs.

Free diagnostic

Where do you stand for GATE?

Take the 20-minute diagnostic: the 3 topics that cost you the most marks, and a rank range. Or sit 5 related Instruction Pipelining PYQs now with no account.

One GATE CSE PYQ every morning

An official question by email at 7 AM IST, with a link to its verified solution. Unsubscribe in one click.

Instruction Pipelining in GATE CSE

Instruction Pipelining has 25 GATE CSE PYQs across 20 papers from 2011 to 2026. 16 of them are 2-mark NAT questions like this one, and it is the only one in GATE CSE 2016 Set 1.

How GATE tests Instruction Pipelining

More from GATE CSE 2016 Set 1

Share this solution

A plain-text card for WhatsApp or Telegram study groups.

GateAI solution cardGATE CSE 2016 Set 1 · Q32 · NAT

The stage delays in a 4-stage pipeline are 800, 500, 400 and 300 picoseconds. The first stage (with delay 800 picoseconds) is replaced with a functionally equivalent design involving two stages with respective delays 600 and 350 picoseconds. The throughput increase of the pipeline is … percent.

Topic-wise GATE CS PYQs with verified steps

Independent practice explanation verified by the GateAI team. GATE is conducted by the IITs; question text follows the official paper.