The width of the physical address on a machine is 40 bits. The width of the tag field in a 512 KB 8-way set associative cache is … bits.
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GATE CSE 2016 Set 2 · Q32
Time
Your answerNumerical answer
Solution
Official answer: 24
Cache Memory and HierarchyLet the cache parameters be:
Cache size
Set associativity
Block size (where is the number of block offset bits)
The number of sets in the cache is:
Therefore, the number of bits required for the Set index field is:
A physical address is divided into three fields:
Substituting the given physical address width ():
Thus, the width of the tag field is 24 bits.
Try the question first, then check your work.
Examiner trap
Note that the sum of the set index bits and block offset bits equals , which is independent of the block size.
This Cache Memory and Hierarchy previous year question is Q32 of the GATE CSE 2016 Set 2 paper. Find more GATE CSE PYQs on Cache Memory and Hierarchy in Computer Organization and Architecture, or browse all GATE CSE PYQs.
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Cache Memory and Hierarchy has 47 GATE CSE PYQs across 23 papers from 2011 to 2026. 16 of them are 2-mark NAT questions like this one, and it is the only one in GATE CSE 2016 Set 2.
How GATE tests Cache Memory and HierarchyIndependent practice explanation verified by the GateAI team. GATE is conducted by the IITs; question text follows the official paper.