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Cache Memory and Hierarchy

GATE CSE 2016 Set 2 · Q32

NAT2 marksMedium

Time

The width of the physical address on a machine is 40 bits. The width of the tag field in a 512 KB 8-way set associative cache is _______ bits.

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Official answer: 24

Cache Memory and Hierarchy

Let the cache parameters be:

  • Cache size C=512 KB=219 bytesC = 512\text{ KB} = 2^{19}\text{ bytes}

  • Set associativity P=8=23P = 8 = 2^3

  • Block size =B=2b bytes= B = 2^b\text{ bytes} (where bb is the number of block offset bits)

The number of sets SS in the cache is:

S=Cache SizeAssociativity×Block Size=21923×2b=216−bS = \frac{\text{Cache Size}}{\text{Associativity} \times \text{Block Size}} = \frac{2^{19}}{2^3 \times 2^b} = 2^{16 - b}

Therefore, the number of bits required for the Set index field is:

Set bits=16−b\text{Set bits} = 16 - b

A physical address is divided into three fields:

Physical Address bits=Tag bits+Set bits+Block offset bits\text{Physical Address bits} = \text{Tag bits} + \text{Set bits} + \text{Block offset bits}

Substituting the given physical address width (40 bits40\text{ bits}):

40=Tag bits+(16−b)+b40 = \text{Tag bits} + (16 - b) + b
40=Tag bits+1640 = \text{Tag bits} + 16
Tag bits=40−16=24\text{Tag bits} = 40 - 16 = 24

Thus, the width of the tag field is 24 bits.

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This Cache Memory and Hierarchy previous year question is Q32 of the GATE CSE 2016 Set 2 paper. Find more GATE CSE PYQs on Cache Memory and Hierarchy in Computer Organization and Architecture, or browse all GATE CSE PYQs.

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Cache Memory and Hierarchy in GATE CSE

Cache Memory and Hierarchy has 47 GATE CSE PYQs across 23 papers from 2011 to 2026. 16 of them are 2-mark NAT questions like this one, and it is the only one in GATE CSE 2016 Set 2.

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GateAI solution cardGATE CSE 2016 Set 2 · Q32 · NAT

The width of the physical address on a machine is 40 bits. The width of the tag field in a 512 KB 8-way set associative cache is … bits.

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