Computer Organization and Architecture · Instruction Pipelining
Official IIT answer key · IISc Bangalore · Audited Aug 2026
GATE CSE 2016 Set 2 Q33 · NAT · 2 marks
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Topic notes
Instruction pipelining and pipeline hazards are tested extensively with a heavy numerical skew (primarily 2-mark NATs). GATE focuses on evaluating effective CPI and speedup under realistic hazard scenarios (data, control, and structural), calculating clock cycle time from bottleneck stage delays and latch latencies, and analyzing cycle-by-cycle instruction progression with or without operand forwarding. Conceptual items frequently test dependency classifications (RAW, WAR, WAW) and the mechanics of operand bypassing.
Full Instruction Pipelining guide →Consider a 3 GHz (gigahertz) processor with a three-stage pipeline and stage latencies au1, au2, and au3 such that au1 = 3 au2/4 = 2 au3. If the longest pipeline stage is split into two pipeline stages of equal latency, the new frequency is … GHz, ignoring delays in the pipeline registers.
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