Computer Organization and Architecture · Cache Memory and Hierarchy
Official IIT answer key · IIT Roorkee · Audited Aug 2026
GATE CSE 2017 Set 1 Q25 · NAT · 1 mark
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Topic notes
Memory hierarchy and cache mapping is one of the highest-yield, most quantitative topics in GATE Computer Science, regularly tested through 2-mark NAT and MSQ questions. GATE focuses heavily on bit-level address field decomposition (Tag, Set/Line Index, Block Offset) across direct, set-associative, and fully-associative caches, as well as multi-level hierarchical Average Memory Access Time (AMAT) calculations. Recent years have increased the emphasis on multi-select questions (MSQs) tracing reference sequences for eviction behavior and comparing write-back versus write-through policies.
Full Cache Memory and Hierarchy guide →Consider a two-level cache hierarchy with L1 and L2 caches. An application incurs 1.4 memory accesses per instruction on average. For this application, the miss rate of L1 cache is 0.1; the L2 cache experiences, on average, 7 misses per 1000 instructions. The miss rate of L2 expressed correct to two decimal places is …
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