In a two-level cache system, the access times of $L_1$ and $L_2$ caches are 1 and 8 clock cycles, respectively. The miss penalty from the $L_2$ cache to main memory is 18 clock cycles. The miss rate of $L_1$ cache is twice that of $L_2$. The average memory access time (AMAT) of this cache system is 2 cycles. The miss rates of $L_1$ and $L_2$ respectively are:

Given parameters:

• $L_1$ cache access time, $t_{L1} = 1$ cycle

• $L_2$ cache access time, $t_{L2} = 8$ cycles

• Miss penalty from $L_2$ to main memory, $P_{L2} = 18$ cycles

• $\text{AMAT} = 2$ cycles

• Miss rate relation: $m_1 = 2 m_2 \implies m_2 = \frac{m_1}{2}$

The formula for Average Memory Access Time (AMAT) for a two-level hierarchical cache system is:

Substitute the given values:

Factorize the quadratic equation:

Since a miss rate must be positive ($m_1 > 0$):

Thus, the miss rates of $L_1$ and $L_2$ are 0.111 and 0.056 respectively, matching Option (A).