GateAI
Cache Memory and Hierarchy

GATE CSE 2018 · Q23

NAT1 markMedium

Time

A 32-bit wide main memory unit with a capacity of 1 GB is built using 256M ×\times 4-bit DRAM chips. The number of rows of memory cells in the DRAM chip is 2142^{14}. The time taken to perform one refresh operation is 50 nanoseconds. The refresh period is 2 milliseconds. The percentage (rounded to the closest integer) of the time available for performing the memory read/write operations in the main memory unit is _______.

Your answerNumerical answer

Enter a value to check

Solution

Step-by-step verified solution

Official answer: 59 (±1) (±1)

Cache Memory and Hierarchy

To maintain DRAM contents, all rows must be refreshed within the refresh period.

  1. Number of rows to refresh:

    Rows=214=16384\text{Rows} = 2^{14} = 16384
  2. Time spent on refreshing during one refresh period:

    Time for one refresh=50 ns\text{Time for one refresh} = 50\text{ ns}
    Trefresh=16384×50 ns=819200 ns=0.8192 msT_{\text{refresh}} = 16384 \times 50\text{ ns} = 819200\text{ ns} = 0.8192\text{ ms}
  3. Refresh period:

    Tperiod=2 msT_{\text{period}} = 2\text{ ms}
  4. Percentage of time spent refreshing:

    Percentageextrefresh=0.8192 ms2 ms×100%=40.96%\text{Percentage}_{ ext{refresh}} = \frac{0.8192\text{ ms}}{2\text{ ms}} \times 100\% = 40.96\%
  5. Percentage of time available for read/write operations:

    Available time percentage=100%−40.96%=59.04%\text{Available time percentage} = 100\% - 40.96\% = 59.04\%

Rounding to the closest integer gives 59 (acceptable range: 59.0 to 60.0).

Try the question first, then check your work.

Think the official key or this write-up is wrong?

Report error or challenge

Examiner trap

The misconception this question tests

This Cache Memory and Hierarchy previous year question is Q23 of the GATE CSE 2018 paper. Find more GATE CSE PYQs on Cache Memory and Hierarchy in Computer Organization and Architecture, or browse all GATE CSE PYQs.

Free diagnostic

Where do you stand for GATE?

Take the 20-minute diagnostic: the 3 topics that cost you the most marks, and a rank range. Or sit 5 related Cache Memory and Hierarchy PYQs now with no account.

One GATE CSE PYQ every morning

An official question by email at 7 AM IST, with a link to its verified solution. Unsubscribe in one click.

Cache Memory and Hierarchy in GATE CSE

Cache Memory and Hierarchy has 47 GATE CSE PYQs across 23 papers from 2011 to 2026. 7 of them are 1-mark NAT questions like this one, and it is the only one in GATE CSE 2018.

How GATE tests Cache Memory and Hierarchy

More from GATE CSE 2018

Share this solution

A plain-text card for WhatsApp or Telegram study groups.

GateAI solution cardGATE CSE 2018 · Q23 · NAT

A 32-bit wide main memory unit with a capacity of 1 GB is built using 256M × 4-bit DRAM chips. The number of rows of memory cells in the DRAM chip is 214. The time taken to perform one refresh operation is 50 nanoseconds. The refresh period is 2 milliseconds. The percentage (rounded to the closest integer) of the time available for performing the memory read/write operations in the main memory unit is …

Topic-wise GATE CS PYQs with verified steps

Independent practice explanation verified by the GateAI team. GATE is conducted by the IITs; question text follows the official paper.