The chip select logic for a certain DRAM chip in a memory system design is shown below. Assume that the memory system has 16 address lines denoted by $A_{15}$ to $A_0$. What is the range of addresses (in hexadecimal) of the memory system that can get enabled by the chip select (CS) signal?

From the given logic diagram, the chip select (CS) output is the output of an AND gate with 5 inputs:

• $A_{15} = 1$

• $A_{14} = 1$

• $A_{13} = 0$ (active-low inverted input)

• $A_{12} = 0$ (active-low inverted input)

• $A_{11} = 1$

Thus, the higher 5 bits $A_{15}A_{14}A_{13}A_{12}A_{11}$ are fixed to $11001_2$.

The remaining 11 address lines ($A_{10}$ to $A_0$) can take any value from all $0$s to all $1$s.

• Minimum Address:

  $$1100\ 1000\ 0000\ 0000_2 = \text{C800}_{16}$$

• Maximum Address:

  $$1100\ 1111\ 1111\ 1111_2 = \text{CFFF}_{16}$$

Therefore, the address range is C800 to CFFF, which corresponds to option (A).