Computer Organization and Architecture · Instruction Set and Addressing Modes
Official IIT answer key · IIT Kanpur · Audited Aug 2026
GATE CSE 2023 Q41 · MCQ · 2 marks
Consider the given C-code and its corresponding assembly code, with a few operands U1–U4 being unknown. Some useful information as well as the semantics of each unique assembly instruction is annotated as inline comments in the code. The memory is byte-addressable.
Key concept
Topic notes
Instruction set and addressing modes in GATE CS is consistently tested through instruction word encoding, expanding opcode schemes, addressing mode semantics, and ISA architectural principles. Problems evaluate a candidate's ability to calculate bit allocations for opcodes, register specifiers, and immediates, as well as mapping high-level constructs (structs, arrays, pointers) to assembly addressing modes. The topic features a healthy mix of conceptual 1-mark MCQs/MSQs and rigorous 2-mark NATs involving bit calculations and assembly program traces.
Full Instruction Set and Addressing Modes guide →Independent practice explanation verified by the GateAI team. GATE is conducted by the IITs; question text follows the official paper.
