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Instruction Pipelining

GATE CSE 2012 · Q20

MCQ1 markEasy

Time

Register renaming is done in pipelined processors

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Solution

Step-by-step verified solution

Official answer: C) to handle certain kinds of hazards

Instruction Pipelining

Register renaming is a technique used in pipelined and superscalar processors to eliminate false data dependencies (hazards), specifically:

  • WAR (Write-After-Read / Anti-dependence)

  • WAW (Write-After-Write / Output dependence)

By dynamically mapping architectural registers to a larger set of physical registers, register renaming eliminates these hazards and allows out-of-order instruction execution.

Hence, option C is correct.

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This Instruction Pipelining previous year question is Q20 of the GATE CSE 2012 paper. Find more GATE CSE PYQs on Instruction Pipelining in Computer Organization and Architecture, or browse all GATE CSE PYQs.

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Instruction Pipelining in GATE CSE

Instruction Pipelining has 25 GATE CSE PYQs across 20 papers from 2011 to 2026. 3 of them are 1-mark MCQs like this one, and it is the only one in GATE CSE 2012.

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GateAI solution cardGATE CSE 2012 · Q20 · MCQ

Register renaming is done in pipelined processors

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Independent practice explanation verified by the GateAI team. GATE is conducted by the IITs; question text follows the official paper.