Register renaming is done in pipelined processors
Topic-wise GATE CS PYQs with verified steps
GATE CSE 2012 · Q20
Time
Select one answerSingle correct
Solution
Official answer: C) to handle certain kinds of hazards
Instruction PipeliningRegister renaming is a technique used in pipelined and superscalar processors to eliminate false data dependencies (hazards), specifically:
WAR (Write-After-Read / Anti-dependence)
WAW (Write-After-Write / Output dependence)
By dynamically mapping architectural registers to a larger set of physical registers, register renaming eliminates these hazards and allows out-of-order instruction execution.
Hence, option C is correct.
Try the question first, then check your work.
Examiner trap
Consider which type of pipeline issues arise due to name dependencies (WAR and WAW hazards).
This Instruction Pipelining previous year question is Q20 of the GATE CSE 2012 paper. Find more GATE CSE PYQs on Instruction Pipelining in Computer Organization and Architecture, or browse all GATE CSE PYQs.
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Instruction Pipelining has 25 GATE CSE PYQs across 20 papers from 2011 to 2026. 3 of them are 1-mark MCQs like this one, and it is the only one in GATE CSE 2012.
How GATE tests Instruction PipeliningIndependent practice explanation verified by the GateAI team. GATE is conducted by the IITs; question text follows the official paper.