Consider the following reservation table for a pipeline having three stages S1, S2 and S3. The minimum average latency (MAL) is …
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GATE CSE 2015 Set 3 · Q51
Time

Your answerNumerical answer
Solution
Official answer: 3
Instruction PipeliningTo determine the Minimum Average Latency (MAL) from the reservation table:
Identify Forbidden Latencies ():
Stage is used at time steps 1 and 5: latency .
Stage is used at time steps 2 and 4: latency .
Stage is used only at time step 3: no collision.
Set of forbidden latencies: .
Initial Collision Vector ():
Since the maximum forbidden latency is 4:
State Transition Diagram / Simple Cycles:
From state :
Allowed latency 1: .
From , only latencies are allowed, leading back to . Cycle: with average latency .
Allowed latency 3: .
From , latency 3 gives . Constant cycle: with average latency .
Minimum Average Latency (MAL):
Both simple cycles and yield an average latency of .
Hence, .
Try the question first, then check your work.
Examiner trap
Find the set of forbidden latencies by taking the difference between time slots in each row. Construct the collision vector and find the simple cycle with the smallest average latency.
This Instruction Pipelining previous year question is Q51 of the GATE CSE 2015 Set 3 paper. Find more GATE CSE PYQs on Instruction Pipelining in Computer Organization and Architecture, or browse all GATE CSE PYQs.
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Instruction Pipelining has 25 GATE CSE PYQs across 20 papers from 2011 to 2026. 16 of them are 2-mark NAT questions like this one, and GATE CSE 2015 Set 3 has 2.
How GATE tests Instruction PipeliningIndependent practice explanation verified by the GateAI team. GATE is conducted by the IITs; question text follows the official paper.