Consider the following processors (ns stands for nanoseconds). Assume that the pipeline registers have zero latency. P1: Four-stage pipeline with stage latencies 1 ns, 2 ns, 2 ns, 1 ns. P2: Four-stage pipeline with stage latencies 1 ns, 1.5 ns, 1.5 ns, 1.5 ns. P3: Five-stage pipeline with stage latencies 0.5 ns, 1 ns, 1 ns, 0.6 ns, 1 ns. P4: Five-stage pipeline with stage latencies 0.5 ns, 0.5 ns, 1 ns, 1 ns, 1.1 ns. Which processor has the highest peak clock frequency?

The clock period ($T$) of a pipelined processor is dictated by the maximum stage latency plus pipeline register delay:

Since the pipeline registers have zero latency:

• P1: $T_1 = \max(1, 2, 2, 1) = 2\text{ ns} \implies f_1 = \frac{1}{2\text{ ns}} = 0.5\text{ GHz} = 500\text{ MHz}$

• P2: $T_2 = \max(1, 1.5, 1.5, 1.5) = 1.5\text{ ns} \implies f_2 = \frac{1}{1.5\text{ ns}} \approx 666.67\text{ MHz}$

• P3: $T_3 = \max(0.5, 1, 1, 0.6, 1) = 1.0\text{ ns} \implies f_3 = \frac{1}{1.0\text{ ns}} = 1.0\text{ GHz} = 1000\text{ MHz}$

• P4: $T_4 = \max(0.5, 0.5, 1, 1, 1.1) = 1.1\text{ ns} \implies f_4 = \frac{1}{1.1\text{ ns}} \approx 909.09\text{ MHz}$

Processor P3 has the smallest clock period ($1.0\text{ ns}$) and hence the highest peak clock frequency ($1\text{ GHz}$).

Therefore, C is the correct option.