Computer Organization and Architecture · Instruction Pipelining
Official IIT answer key · IIT Kharagpur · Audited Aug 2026
GATE CSE 2014 Set 1 Q43 · NAT · 2 marks
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Topic notes
Instruction pipelining and pipeline hazards are tested extensively with a heavy numerical skew (primarily 2-mark NATs). GATE focuses on evaluating effective CPI and speedup under realistic hazard scenarios (data, control, and structural), calculating clock cycle time from bottleneck stage delays and latch latencies, and analyzing cycle-by-cycle instruction progression with or without operand forwarding. Conceptual items frequently test dependency classifications (RAW, WAR, WAW) and the mechanics of operand bypassing.
Full Instruction Pipelining guide →Consider a 6-stage instruction pipeline, where all stages are perfectly balanced. Assume that there is no cycle-time overhead of pipelining. When an application is executing on this 6-stage pipeline, the speedup achieved with respect to non-pipelined execution if 25% of the instructions incur 2 pipeline stall cycles is …
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