Consider an instruction pipeline with four stages (S1, S2, S3 and S4) each with combinational circuit only. The pipeline registers are required between each stage and at the end of the last stage. Delays for the stages and for the pipeline registers are as given in the figure. What is the approximate speed up of the pipeline in steady state under ideal conditions when compared to the corresponding non-pipeline implementation?

1. Execution time in the non-pipelined processor ($T_{\text{non-pipe}}$): In a non-pipelined system, there are no pipeline registers, and the total execution time is the sum of the delays of all combinational stages:

   $$T_{\text{non-pipe}} = 5\text{ ns} + 6\text{ ns} + 11\text{ ns} + 8\text{ ns} = 30\text{ ns}$$

2. Clock cycle time in the pipelined processor ($T_{\text{pipe}}$): The clock cycle time is determined by the stage with the maximum delay (bottleneck stage) plus the pipeline register delay:

   $$T_{\text{pipe}} = \max(5, 6, 11, 8)\text{ ns} + 1\text{ ns} = 11\text{ ns} + 1\text{ ns} = 12\text{ ns}$$

3. Speedup ($S$) in steady state: Under ideal steady-state conditions, the pipeline completes one instruction per clock cycle (CPI = 1):

   $$\text{Speedup } S = \frac{T_{\text{non-pipe}}}{T_{\text{pipe}}} = \frac{30\text{ ns}}{12\text{ ns}} = 2.5$$

Thus, the speed up is 2.5, which matches option (B).