Consider the following code sequence having five instructions $I_1$ to $I_5$. Each of these instructions has the following format. OP Ri, Rj, Rk where operation OP is performed on contents of registers Rj and Rk and the result is stored in register Ri. $I_1$: ADD R1, R2, R3 $I_2$: MUL R7, R1, R3 $I_3$: SUB R4, R1, R5 $I_4$: ADD R3, R2, R4 $I_5$: MUL R7, R8, R9 Consider the following three statements. S1: There is an anti-dependence between instructions $I_2$ and $I_5$ S2: There is an anti-dependence between instructions $I_2$ and $I_4$ S3: Within an instruction pipeline an anti-dependence always creates one or more stalls Which one of above statements is/are correct?

Let us analyze the read and write sets for each instruction based on the format OP Ri, Rj, Rk (where Ri is written, and Rj, Rk are read):

• $I_1$: Writes R1, Reads R2, R3

• $I_2$: Writes R7, Reads R1, R3

• $I_3$: Writes R4, Reads R1, R5

• $I_4$: Writes R3, Reads R2, R4

• $I_5$: Writes R7, Reads R8, R9

Definitions of Data Dependences:

• True Data Dependence (RAW): An instruction reads a value written by an earlier instruction.

• Anti-dependence (WAR): An instruction writes to a register that is read by an earlier instruction.

• Output dependence (WAW): An instruction writes to a register that is also written by an earlier instruction.

Statement Analysis:

1. S1: Between $I_2$ (writes R7) and $I_5$ (writes R7), both write to the same register R7. This is an output dependence (WAW), not an anti-dependence. Thus, S1 is FALSE.

2. S2: Instruction $I_2$ reads register R3, while subsequent instruction $I_4$ writes to register R3. This constitutes a Write-After-Read (WAR) relation, which is an anti-dependence. Thus, S2 is TRUE.

3. S3: In a typical in-order pipeline (like the standard 5-stage RISC pipeline), operands are read in the Instruction Decode (ID) stage and written in the Write Back (WB) stage. Since instructions flow in order, reading occurs before the write-back of a subsequent instruction; thus, anti-dependencies do not cause stalls. In out-of-order execution, WAR hazards can also be eliminated using register renaming without stalls. Thus, S3 is FALSE.

Therefore, only statement S2 is true, which corresponds to option (B).