Consider a non-pipelined processor operating at 2.5 GHz. It takes 5 clock cycles to complete an instruction. You are going to make a 5-stage pipeline out of this processor. Overheads associated with pipelining force you to operate the pipelined processor at 2 GHz. In a given program, assume that 30% are memory instructions, 60% are ALU instructions and the rest are branch instructions. 5% of the memory instructions cause stalls of 50 clock cycles each due to cache misses and 50% of the branch instructions cause stalls of 2 cycles each. Assume that there are no stalls associated with the execution of ALU instructions. For this program, the speedup achieved by the pipelined processor over the non-pipelined processor (round off to 2 decimal places) is _________.

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Official answer: 2.16 (±0.02) (±0.02)

Instruction Pipelining

### 1. Non-pipelined processor execution time per instruction ( $T_{\text{non-pipe}}$ ):

\text{Frequency} = 2.5\text{ GHz} \implies \text{Clock cycle time } t_{\text{non-pipe}} = \frac{1}{2.5\text{ GHz}} = 0.4\text{ ns}

\text{Cycles per instruction (CPI)}_{\text{non-pipe}} = 5

T_{\text{non-pipe}} = \text{CPI}_{\text{non-pipe}} \times t_{\text{non-pipe}} = 5 \times 0.4\text{ ns} = 2.0\text{ ns}

### 2. Pipelined processor execution time per instruction ( $T_{\text{pipe}}$ ):

\text{Frequency} = 2\text{ GHz} \implies \text{Clock cycle time } t_{\text{pipe}} = \frac{1}{2\text{ GHz}} = 0.5\text{ ns}

Instruction mix:

Memory instructions = $30\% = 0.30$
ALU instructions = $60\% = 0.60$
Branch instructions = $100\% - (30\% + 60\%) = 10\% = 0.10$

Stall cycles per instruction:

Memory stalls = $0.30 \times 0.05 \times 50 = 0.75$ cycles
Branch stalls = $0.10 \times 0.50 \times 2 = 0.10$ cycles
ALU stalls = $0$ cycles

\text{Total average stall cycles} = 0.75 + 0.10 = 0.85\text{ cycles}

\text{CPI}_{\text{pipe}} = 1 + \text{Stall cycles} = 1 + 0.85 = 1.85

T_{\text{pipe}} = \text{CPI}_{\text{pipe}} \times t_{\text{pipe}} = 1.85 \times 0.5\text{ ns} = 0.925\text{ ns}

### 3. Speedup calculation:

\text{Speedup} = \frac{T_{\text{non-pipe}}}{T_{\text{pipe}}} = \frac{2.0\text{ ns}}{0.925\text{ ns}} \approx 2.16216...

Rounding off to 2 decimal places gives 2.16 (official range: 2.15 to 2.18).

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This Instruction Pipelining previous year question is Q43 of the GATE CSE 2020 paper. Find more GATE CSE PYQs on Instruction Pipelining in Computer Organization and Architecture, or browse all GATE CSE PYQs.

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Instruction Pipelining in GATE CSE

Instruction Pipelining has 25 GATE CSE PYQs across 20 papers from 2011 to 2026. 16 of them are 2-mark NAT questions like this one, and it is the only one in GATE CSE 2020.

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Independent practice explanation verified by the GateAI team. GATE is conducted by the IITs; question text follows the official paper.