Consider a pipelined processor with 5 stages, Instruction Fetch (IF), Instruction Decode (ID), Execute (EX), Memory Access (MEM), and Write Back (WB). Each stage of the pipeline, except the EX stage, takes one cycle. Assume that the ID stage merely decodes the instruction and the register read is performed in the EX stage. The EX stage takes one cycle for ADD instruction and two cycles for MUL instruction. Ignore pipeline register latencies. Consider the following sequence of 8 instructions: $$\text{ADD, MUL, ADD, MUL, ADD, MUL, ADD, MUL}$$ Assume that every MUL instruction is data-dependent on the ADD instruction just before it and every ADD instruction (except the first ADD) is data-dependent on the MUL instruction just before it. The $\textit{Speedup}$ is defined as follows: $$\text{Speedup} = \frac{\text{Execution time without operand forwarding}}{\text{Execution time with operand forwarding}}$$ The $\textit{Speedup}$ achieved in executing the given instruction sequence on the pipelined processor (rounded to 2 decimal places) is \underline{$\hspace{1.5cm}$}.

Let the 8 instructions be labeled as $I_1$ (ADD), $I_2$ (MUL), $I_3$ (ADD), $I_4$ (MUL), $I_5$ (ADD), $I_6$ (MUL), $I_7$ (ADD), and $I_8$ (MUL).

Since register read occurs in the EX stage:

### 1. Without Operand Forwarding A dependent instruction must wait until the producing instruction writes its result back in the WB stage. Thus, the dependent instruction's EX stage can only start in the cycle after the preceding instruction completes WB.

• $I_1$ (ADD): $\text{EX} = 3$, $\text{MEM} = 4$, $\text{WB} = 5$ (completes at cycle 5)

• $I_2$ (MUL): $\text{EX}_1 = 6, \text{EX}_2 = 7$, $\text{MEM} = 8$, $\text{WB} = 9$ (completes at cycle 9)

• $I_3$ (ADD): $\text{EX} = 10$, $\text{MEM} = 11$, $\text{WB} = 12$ (completes at cycle 12)

• $I_4$ (MUL): $\text{EX}_1 = 13, \text{EX}_2 = 14$, $\text{MEM} = 15$, $\text{WB} = 16$ (completes at cycle 16)

• $I_5$ (ADD): $\text{EX} = 17$, $\text{MEM} = 18$, $\text{WB} = 19$ (completes at cycle 19)

• $I_6$ (MUL): $\text{EX}_1 = 20, \text{EX}_2 = 21$, $\text{MEM} = 22$, $\text{WB} = 23$ (completes at cycle 23)

• $I_7$ (ADD): $\text{EX} = 24$, $\text{MEM} = 25$, $\text{WB} = 26$ (completes at cycle 26)

• $I_8$ (MUL): $\text{EX}_1 = 27, \text{EX}_2 = 28$, $\text{MEM} = 29$, $\text{WB} = 30$ (completes at cycle 30)

### 2. With Operand Forwarding With operand forwarding, the result is available directly at the end of the EX stage to the EX stage of the next instruction:

• $I_1$ (ADD): $\text{EX} = 3$ (result ready at end of cycle 3)

• $I_2$ (MUL): $\text{EX}_1 = 4, \text{EX}_2 = 5$ (result ready at end of cycle 5)

• $I_3$ (ADD): $\text{EX} = 6$ (result ready at end of cycle 6)

• $I_4$ (MUL): $\text{EX}_1 = 7, \text{EX}_2 = 8$ (result ready at end of cycle 8)

• $I_5$ (ADD): $\text{EX} = 9$ (result ready at end of cycle 9)

• $I_6$ (MUL): $\text{EX}_1 = 10, \text{EX}_2 = 11$ (result ready at end of cycle 11)

• $I_7$ (ADD): $\text{EX} = 12$ (result ready at end of cycle 12)

• $I_8$ (MUL): $\text{EX}_1 = 13, \text{EX}_2 = 14$, $\text{MEM} = 15$, $\text{WB} = 16$ (completes at cycle 16)

### 3. Speedup Calculation