Loading previous year questions
Computer Organization and Architecture · Instruction Pipelining
Official IIT answer key · IIT Roorkee · Audited Aug 2026
GATE CSE 2026 Set 1 Q16 · MCQ · 1 mark
Key concept
No account needed
Sit 5 related Instruction PipeliningPYQs as a guest. We'll score the set and show which traps cost marks — sign in only if you want to save the run.
Explore all 109 Computer Organization and Architecture questions
Topic notes
Instruction pipelining and pipeline hazards are tested extensively with a heavy numerical skew (primarily 2-mark NATs). GATE focuses on evaluating effective CPI and speedup under realistic hazard scenarios (data, control, and structural), calculating clock cycle time from bottleneck stage delays and latch latencies, and analyzing cycle-by-cycle instruction progression with or without operand forwarding. Conceptual items frequently test dependency classifications (RAW, WAR, WAW) and the mechanics of operand bypassing.
Full Instruction Pipelining guide →Which one of the following dependencies among the register operands of different instructions can cause a data hazard in a pipelined processor?
Topic-wise GATE CS PYQs with verified steps
Independent practice explanation verified by the GateAI team. GATE is conducted by the IITs; question text follows the official paper.