Which one of the following dependencies among the register operands of different instructions can cause a data hazard in a pipelined processor?

A data hazard occurs when instructions that exhibit data dependence modify or access registers in different pipeline stages, leading to incorrect execution if the order of operations is not preserved.

• Read-After-Write (RAW): This represents a true data dependency where instruction $j$ tries to read a source register before instruction $i$ writes to it. If $j$ reads the register before $i$ completes its write stage, $j$ gets stale data, creating a RAW hazard.

• Read-After-Read (RAR): Reading the same register multiple times never modifies data, so it cannot cause a hazard.

• Write-After-Read (WAR) and Write-After-Write (WAW): These are name dependencies (anti-dependence and output dependence) that only cause hazards in out-of-order execution pipelines with variable execution latencies, but RAW is the fundamental true data dependency causing data hazards in pipelined execution.

Therefore, Read-after-write is the correct option.